1. Field of the Invention
The present invention is directed to an internal voltage control method and apparatus in a semiconductor memory device and more particularly, to method and apparatus which reliably operate a volatile semiconductor memory and reduce current surges through internal circuits in the volatile semiconductor memory when entering, exiting, or operating in a power down mode.
2. Discussion of Related Art
It has long been a goal for semiconductor memory designers to design higher cell capacity and faster semiconductor memories that also consume less power. Since Dynamic Random Access Memories (DRAMs) have a smaller cell size than Static Random Access Memories (SRAMs) and thus offer more memory capacity for a given chip size than SRAMs, usage of DRAMs may be preferred in electronic devices having space limitations. However, DRAMs require constant refreshing and draw much more current than SRAMs. For use in a portable or mobile device, the smaller size advantage of DRAMs disappears if a larger battery is needed or if the battery requires constant recharging. As mobile devices are equipped with increased sophistication and functions, demand for increased memory capacity naturally is also increased. Therefore, low power DRAMs are very much in demand.
Various circuits have been designed to reduce DRAM power consumption. For example, when the DRAMs are not operating in active mode, the DRAMs are put in standby or power down modes in which less or minimal current is provided to refresh or hold DRAM data. U.S. Pat. No. 6,058,063 to Jang (the ""063 patent) discloses a circuit for operating memory devices during standby or power-down mode. An external clock enable signal (CKE) is used to signal power-down mode and cut off power to certain circuits such as input buffers. FIG. 1A shows a circuit described in the ""063 patent. A power down signal PBPUB derived from CKE goes from a low level to a high level to signal power down. PBPUB disconnects VCC by switching off Transistor 31 and pulls the output to ground by turning on Transistor 32. The disclosure of the ""063 patent is incorporated by reference herein.
Recently, several DRAM manufacturers made proposals to JEDEC (Joint Electron Device Engineering Council) to standardize the use of a deep power down (DPD) signal for controlling entry and exit to and from a DPD operation mode in DRAMs. Proposals have been made to use the DPD signal to power down DRAMs when they are not in use, thus reducing power consumption.
Protocols for signaling DPD entry and exit modes proposed to JEDEC are shown in FIGS. 1B and 1C. FIG. 1B shows the protocol for DPD entry mode, wherein the DRAM is entering a deep power down mode. As shown in FIG. 1B, a DPD entry mode is signaled when a clock enable (CKE) signal, chip select (CS) signal, write enable (WE) signal go low, and row and column address strobe (/RAS and /CAS) signals stay high, triggered by a low to high CLOCK signal. FIG. 1C signals DPD exit. As shown, DPD exit mode is signaled when clock enable (CKE) goes high, triggered by a low to high CLOCK signal. As shown, the other signals do not affect DPD exit. It is understood that the protocol shown in FIGS. 1B and 1C are merely illustrative and variations to the protocol can be used or adopted for purposes of signaling power down entry and exit. For example, any or all of the control signals such as WE and CAS can have signal levels reversed from that shown or may not even be used to trigger CKE. Any equivalent clock enable signal can serve as CKE to invoke DPD entry and exit.
The proposed use of DPD is to power down the DRAM when the DRAM is not in active usage. Thus, upon entry in DPD mode, the various internal power voltage generators for supplying voltages such as cell capacitor plate voltage, internal array power voltage, internal peripheral power voltage, reference power voltage, etc. to internal circuits of the DRAM are turned off. Also turned off are nearly all the input buffers of the DRAM, except an auxiliary input buffer which will be kept on to receive the DPD exit mode signal.
In implementing DPD entry and exit, a large amount of input buffers and internal voltage generators are turned on and off at substantially the same time. This causes a large amount of current surging through the DRAM. A large current surge causes severe strain on the battery, generate heat and may render a circuit inoperable. Further, certain nodes in circuits turned off may be floating at unspecified voltages and if the circuits are not turned on properly, false triggering of internal circuitry of the DRAM may also occur.
Accordingly, a need exists for a device and method for implementing DPD entry and exit with minimal current surges. A need also exists for a method and device for preventing false triggering of circuits when the DRAM is operating during, entering or exiting DPD mode.
A semiconductor memory device capable of operation in Deep Power Down (DPD) mode, comprising a first transistor controlled by a DPD signal to apply bias voltage to a voltage control device; a second transistor controlled by the DPD signal to apply ground voltage to an output node of the voltage control device; and delay circuit for delaying the DPD signal to produce a delayed version of the DPD signal for selectively delaying the switching on and off of the first and second transistors.
Preferably, when the delayed version of DPD signal is applied the first transistor will disconnect the bias voltage from the voltage control device for a duration before and after the second transistor applies ground voltage to the output node of the voltage control device.
A semiconductor device is also provided for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory, a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level, wherein the maximum current level is the current drawn by the semiconductor memory when the plurality of voltage generators switch from off to on or on to off at substantially the same time. The semiconductor memory is preferably a DRAM.
Preferably, the circuitry includes at least one drive transistor in each of the plurality of voltage generators for driving respective voltage generators to operating voltage levels when entering or exiting DPD mode, wherein the at least one drive transistor in each generator has drive capability different from other drive transistors to provide varied amount of current through the voltage generators when entering or exiting DPD mode.
According to another aspect of the invention, the circuitry includes at least one drive transistor in each of the plurality of voltage generators for driving respective voltage generators to operating voltage levels when entering or exiting DPD mode, and drive transistor control circuit for first turning on the at least one drive transistor in one of the plurality of voltage generators and then followed by turning on the drive transistors in the other voltage generators when entering or exiting DPD mode.
In one preferred embodiment, the circuitry includes a plurality of buffers, each connected to a respective voltage generator and each having a delay for delaying turning on/off corresponding voltage generators at different times according to the delay values of buffers when entering to and exiting from DPD mode, wherein the plurality of buffers include varying sizes of resistors and capacitors.
Alternatively, the circuitry includes a plurality of delay elements connected to the plurality of voltage generators for turning on/off the plurality of voltage generators at different times when entering or exiting DPD mode, wherein the plurality of delay elements are a plurality of buffers, each having an intrinsic delay, connected in series to one another, and each of the plurality of voltage generators is connected to a different output of the plurality of buffers.
A method is also provided for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising, providing operating voltages to the semiconductor memory during active operation and cutting off operating voltages during DPD, detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory, and variably turn on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level, wherein the maximum current level is the current drawn by the semiconductor memory when the plurality of voltage generators switch from off to on or on to off at substantially the same time.
According to still another aspect of the invention, a semiconductor device is provided for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising means for providing operating voltages to the semiconductor memory during active operation and cutting off operating voltages during DPD, means for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory, and means for controlling the application of operating voltages to the semiconductor upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.
The means for controlling includes a first transistor controlled by a first DPD signal to apply to bias voltage (VCC) to an operating voltage output node and a second transistor controlled by a second DPD signal for connecting ground (VSS) to the operating voltage output node, wherein the first DPD signal and the second DPD signal are selectively applied to the first transistor and the second transistor to prevent the first and second transistor from being turned-on at the same time.
Another method is provided for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising providing operating voltages to the semiconductor memory during active operation and cutting off operating voltages during DPD, controlling a first transistor by a first DPD signal to apply a bias voltage (VCC) to an operating voltage output node, controlling a second transistor by a second DPD signal for connecting ground (VSS) to the operating voltage output node, wherein the first DPD signal and the second DPD signal are selectively applied to the first transistor and the second transistor to prevent the first and second transistor from being turned-on at the same time.
Preferably, the first DPD signal and the second DPD signal are generated with logic gates and delay elements, the first DPD signal and the second DPD signal being delayed versions of the DPD signal, wherein the second DPD signal transitions from low to high after a predetermined delay from the transition from low to high of the first DPD signal, wherein the logic gates and delay element include a two-input NAND gate and a two-input NOR gate, wherein each of the two-input NAND gate and two input NOR gate receive as inputs the DPD signal and a delayed version of the DPD signal through a respective first delay element and second delay element, the first delay element and the second delay element having different predetermined delay values.
The method preferably further including the step of controlling at least one-third transistor by the first DPD signal through a turn-on delay element wherein the first transistor is first turned on by the first DPD signal to apply the bias voltage (VCC) to the operating voltage output node when exiting DPD and the at least one third transistor is turned on by the first DPD signal after a turn-on delay provided by the turn-on delay element to increase drive capacity at the operating voltage output node.